Logic Gate

A logic gate is a device or abstract circuit element that implements a Boolean operation, producing an output from one or more binary inputs. Its logical behavior is described using Boolean algebra, while its physical implementation usually uses electronic switches. Gates form the building blocks of digital computers, from arithmetic circuits to control systems. An elementary gate is normally treated as a memoryless component: once its inputs have settled and its response delay has elapsed, its output depends on the current input combination. (ocw.mit.edu)

Binary signals and logical descriptions

Each input or output represents a bit, conventionally written as 0 or 1. These values can denote false and true in propositional logic, or encode information within a binary number. In electronic circuits, they correspond to specified voltage ranges rather than perfectly exact voltages. Under positive logic, the higher voltage range represents 1 and the lower range represents 0; the intervening range is not guaranteed to represent either valid state. (ocw.mit.edu)

A gate’s truth table lists its output for every possible input combination. For $n$ binary inputs, there are $2^n$ combinations. A single-output gate can therefore implement one of $2^{2^n}$ Boolean functions; with two inputs, there are 16 possibilities. A Boolean expression gives an equivalent algebraic description, separating the intended operation from the technology used to realize it. (ocw.mit.edu)

Principal gate types

The most familiar operations are AND, OR, and NOT, together with their inverted variants and equality-related operations. For two inputs $A$ and $B$, the principal functions are:

NOT, also called an inverter, has one input and produces its complement: $\neg0=1$ and $\neg1=0$. A buffer preserves the logical value while providing an electrical driving function. Exclusive OR differs from inclusive OR because its two-input output is 0 when both inputs are 1. (ocw.mit.edu)

AND and OR extend naturally to multiple inputs: a multi-input AND requires every input to be 1, whereas OR requires at least one. NAND and NOR complement those results. Importantly, cascading two-input NAND gates does not automatically produce a multi-input NAND, because NAND is not associative. Cascaded XOR operations instead produce 1 when an odd number of inputs are 1, making them useful for parity calculations. (ocw.mit.edu)

Universal gates and circuit construction

A set of operations is functionally complete if it can express every Boolean function. AND, OR, and NOT together satisfy this condition. NAND alone and NOR alone are also functionally complete, so each is called a universal gate. This means that networks of gates of either type—not a single gate by itself—can realize arbitrary Boolean functions. (ocw.mit.edu)

For example, joining both inputs of a NAND gate to $A$ gives $\neg(A\land A)=\neg A$. Inverting a NAND output produces AND; applying De Morgan’s laws allows OR to be constructed from NAND gates as well. Such identities support circuit transformation without changing logical behavior. (ocw.mit.edu)

A combinational circuit connects gates so that outputs are functions of present inputs, without stored state. Examples include selectors, decoders, and adders. For a half adder, XOR generates the sum bit and AND generates the carry bit, illustrating how elementary gates implement arithmetic. Boolean simplification can reduce hardware, although the smallest expression is not necessarily the fastest or least susceptible to transient glitches. (computationstructures.org)

Electronic implementation

Electronic gates commonly use transistors fabricated in semiconductor material within an integrated circuit. In complementary metal–oxide–semiconductor technology, complementary networks of n-channel and p-channel MOSFETs connect the output toward ground or the supply voltage according to the inputs. A basic CMOS inverter uses one transistor of each type. (ocw.mit.edu)

In conventional static CMOS, a two-input NAND uses series n-channel transistors in its pull-down network and parallel p-channel transistors in its pull-up network. A NOR reverses these arrangements. AND and OR commonly add an inverter after NAND or NOR. Consequently, logically similar operations can have different transistor counts, loading, and delays. (computationstructures.org)

Other implementations include bipolar transistor logic families. Gates sharing a truth table are not necessarily electrically interchangeable: supply ranges, input thresholds, output drive, and switching characteristics must also match. (ti.com)

Timing, loading, and power

Physical gates are not instantaneous. Propagation delay specifies the interval between an input transition and the corresponding output response. Delay depends on operating conditions and output loading. Unequal delays along converging paths can create short-lived output changes, called glitches, even when the final Boolean result is correct. (ti.com)

Fan-in is the number of gate inputs; fan-out describes the downstream load an output can drive. Noise margins express the separation between guaranteed output levels and required input levels, allowing some voltage disturbance without loss of logical interpretation. These electrical constraints accompany, rather than replace, the truth-table specification. (ti.com)

CMOS switching consumes energy as capacitances charge and discharge. Dynamic power depends on switching activity, capacitance, frequency, and supply voltage. Real devices also consume static power through leakage, despite the ideal switch model predicting no steady-state current. (ocw.mit.edu)

Gates and stored state

Connecting gates through feedback can create sequential circuits, whose behavior depends on stored state as well as present inputs. Cross-coupled gates can form a latch; suitably controlled storage structures form flip-flops. Such elements provide memory and support registers and state machines. Their timing requirements differ from those of an isolated combinational gate, because correct operation also depends on when inputs are captured. (ocw.mit.edu)